The ability to dope polysilicon gates to different degrees allows one to adjust the work function of gate electrode materials to particular types of metal oxide silicon (MOS) transistors. It is desirable to adjust the work function of a gate electrode (hereinafter, the gate), to be close to either the conduction band or the valence band of silicon, because this reduces the threshold voltage (Vt) of the transistor, thereby facilitating a high drive current at low operating voltages. For instance, dual work function gates, for example doped polysilicon are advantageously used in microelectronic devices, such as complementary metal oxide silicon (CMOS) transistor devices, having both pMOS and nMOS transistors. The use of doped polysilicon gates has become problematic, however, as the dimensions of gates and gate insulators alike have significantly reduced.
It is well understood that polysilicon gates can accommodate only a finite amount of dopants. This limitation can result in a depletion of gate charge carriers at the interface between the gate and gate dielectric, when the gate is biased to invert the channel. Consequently, the electrical thickness of the gate stack is substantially increased, thereby deteriorating the performance characteristics of the transistor, such as reducing the drive current and slowing switching speeds. For instance, the effective electrical thickness of a gate dielectric in some pMOS transistors can increase from about 1.0 nanometer during accumulation mode, to about 1.8 nanometers during inversion mode. Depletion of the polysilicon gate is a fundamental issue that limits further scaling of MOS devices.
In addition, when high-k gate dielectrics are used with polysilicon a Vt offset of up to 700 mV is observed for pMOS devices depending on the composition of the high-k gate dielectric. This large Vt offset is still not clearly understood but is believed to be associated with dopant (e.g., boron) diffusion and interaction with the gate dielectric and Fermi level pinning as a result of defect creation between the gate and the dielectric. At present, there is no effective way to control this Vt offset problem.
In view of the shortcomings of doped polysilicon in view of today's device sizes, metal gates are an attractive alternative to polysilicon because they have larger supply of charge carriers than doped polysilicon gates. When a metal gate is biased to invert the channel, there is no substantial depletion of carriers at the interface between the metal gate and gate dielectric. Accordingly, the transistor's performance is not deteriorated because the electrical thickness of the gate stack is not increased. In the manufacture of microelectronic devices, having independently adjustable dual work function metal gates has been troublesome, however.
Ideally, dual work function metal gates should be compatible with the type of device in which it will operate. If it is an nMOS gate, then its work function needs to be a work function that is compatible for an nMOS device. If on the other hand, the gate is intended to be a gate for a pMOS device, then its work functions needs to a work function that is compatible for a pMOS device. However, during fabrication processes and due primarily to the thermal budgets involved, the work function of each of these metal gates may shift or drift either up or down, thereby changing the work function and consequently, device performance.
Devices created using the conventional process flow that can also be referred to as gate first process flow allow a high quality gate dielectric to remain intact, but the gates manufactured under such processes suffer from potential work function drift because of potential degradation of the gate dielectric/gate interface upon exposure to high thermal budgets (e.g., those in excess of 700 degrees Celsius) to which it is subjected. To avoid the effects associated with these thermal budgets, manufacturers have developed gate last processes where the gate is formed after the high thermal budgets have been done. Unfortunately, however, during their fabrication, the gate dielectric is typically removed when the dummy gate is removed to form the metal gate electrode. In such instances, the gate dielectric has to be regrown or deposited but done so under lower formation temperatures so as not to disturb the source/drain implants that have already been formed. This process results in a lower quality gate dielectric. Thus, presently, the industry is left with the choice of either having a high quality gate dielectric and contending with work function drift or having a gate dielectric with a more stable work function but a lower quality gate dielectric. Neither of these choices are desirable in view of the demands for higher quality devices that operate at high speed and with greater efficiency.
Accordingly, what is needed in the art is a method of manufacturing microelectronic devices that avoid the disadvantages associated with the current manufacturing processes.